Lecture by Prof. Sanjay Patel, UIUC
Today I attended a lecture by Prof. Sanjay Patel, famous Prof in Comp Arch from UIUC...
Crux: a 1000+ core architecture
Motivation:
Some real-time apps
Main processor can delegate some work to it !
Implementation:
As of now as a co-processor type thing, which has lots of threads, has a different program or thread model !
How did they come up with the design?
Choose the benchmark apps !
Interestingly, to figure out implementation, fed these apps and some hardware parameters, like
Issue Width:
L1 Cache Size:
L2 Cache Size:
CPU Frequency etc
To an optimizer, which then analyses these apps against these hardware choices :
Result: a plot on the AREA vs Performance curve for each of these configs
Final result choose the design that looks reasonable !
Then decision about the programming / thread model and SIMD vs MIMD model
Again benchmark apps, analyze the dependency graphs for these apps ... You can use any tool like PIN easily to figure out this dependency graphs and things like RAW, WAW kind of parameters!
Thus they decided that the Read after Write in one interval of the thread is not too many and they choose to make that case INCORRECT for their model ... ofcourse arguing that this is not the common case ! So optimize the common case is the principle..
Finally they had their thread model called as RTM (Rigel Thread Model, I guess).
Rigel Website:
I think the takeaway for the future architects here is the methodology, the way they came up with the micro-architecture design and how they validated it, clearly stating the benchmarks, even figuring out the power consumption of the final chip (in 45nm)..
One more thing: In the end I was stupidly thinking about asking why he choose to put different I-Cahce for each of the mickey-mouse processor... Then I realized Prof. Dahlin's lecture about picking up the important idea ... So I think even while asking questions, I could have used the idea of focusing on the real issue, rather than cribbing about some nitty-gritty detail!
Thats like real work !
Crux: a 1000+ core architecture
Motivation:
Some real-time apps
Main processor can delegate some work to it !
Implementation:
As of now as a co-processor type thing, which has lots of threads, has a different program or thread model !
How did they come up with the design?
Choose the benchmark apps !
Interestingly, to figure out implementation, fed these apps and some hardware parameters, like
Issue Width:
L1 Cache Size:
L2 Cache Size:
CPU Frequency etc
To an optimizer, which then analyses these apps against these hardware choices :
Result: a plot on the AREA vs Performance curve for each of these configs
Final result choose the design that looks reasonable !
Then decision about the programming / thread model and SIMD vs MIMD model
Again benchmark apps, analyze the dependency graphs for these apps ... You can use any tool like PIN easily to figure out this dependency graphs and things like RAW, WAW kind of parameters!
Thus they decided that the Read after Write in one interval of the thread is not too many and they choose to make that case INCORRECT for their model ... ofcourse arguing that this is not the common case ! So optimize the common case is the principle..
Finally they had their thread model called as RTM (Rigel Thread Model, I guess).
Rigel Website:
I think the takeaway for the future architects here is the methodology, the way they came up with the micro-architecture design and how they validated it, clearly stating the benchmarks, even figuring out the power consumption of the final chip (in 45nm)..
One more thing: In the end I was stupidly thinking about asking why he choose to put different I-Cahce for each of the mickey-mouse processor... Then I realized Prof. Dahlin's lecture about picking up the important idea ... So I think even while asking questions, I could have used the idea of focusing on the real issue, rather than cribbing about some nitty-gritty detail!
Thats like real work !
Isnt Sanjay Patel hot?
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